In most conventional data processing systems the central processor unit thereof is generally arranged to operate synchronously with the memory units of the system at a synchronous rate which is related to the speed of operation of the memory unit with which it is used. The memory functions are controlled by the central processor unit (CPU) and the two units are then synchronously operated by the use of appropriate timing signals communicated therebetween.
In such apparatus the data processing system functions by transferring data among its internal registers, its memory, and its input-output (I/O) devices, which data transfer involves movements of data between a source and a destination either directly or through intervening units, such as an arithmetic logic unit (ALU), which appropriately modify the date which is being transferred. In such cases the data transfers with I/O devices occur over a bi-directional I/O bus while data transfers with memory usually occur over a bi-directional memory bus. In addition, the apparatus has an appropriate independent memory address bus for transferring memory address data.
Operation of the CPU asynchronously with the memory unit permits the CPU to be adapted for use with a plurality of different memory systems each of which may operate at a different speed, independently of the speed of operation of the CPU. The memory units can then be arranged so as to be capable of performing their own functions without regard to the internal operating speed of the CPU.